FELIS Architecture


Click here for the FELIS brochure (PDF)

FELIS consists of video I/O blocks, programming I/O blocks, external RAM interfaces and various image processors. All blocks are modular, much like toy building bricks. Some of the realized image processors are:

  • 2D FIR (Finite Impulse Response) filter (convolution),
  • median filter,
  • dilation and erosion operators,
  • color-space converter
  • CNN (Cellular Neural Network) emulator,
  • histogram calculator,
  • image histogram adjuster,
  • 2D band-pass filter (Gabor filter),
  • image line buffer,
  • boundary condition generator.

The structure of FELIS is designed at schematic level, coded in VHDL and realized on FPGAs. The VHDL codes are not dependent on any FPGA manufacturer except for the I/O blocks. The system is reliable and fast with its schematic design. It is also possible to modify the design for ASIC.

Please contact us at info@felislab.com for more information.